Gold plated 25-30 micro-inches of hard gold (standard).Tin or solder plating is available.Contact surface can be refurbished.
100's of thousands of insertions without measurable degradation in signal integrity.
As little as 10 grams force requirement to achieve connection.
Current handling for 10 mil diameter pad is ~15 amps.
No inductance, no capacitance, ~1 % increase in impedance.
(CDP) Material can be designed to withhold up to 26 G's of shock and vibration.
Temperature dependence is determined by the substrate material:
-40C to 150C for FR4
-60C to 200C for Kapton film
-250C to 400C on crystalline (Ceramic or Silicon) substrate.
Contact point size is 4um; .4mm pitch can be achieved.
RoHs compliance - lead free
Ability to solder or glue substrate to PCB for permanent connection using patented Diamond Adhesive Technology
How Diamond Plating Improves System Interconnect Return Loss
SEM of Diamonds Making Contact with Solder Ball
The Conductive Diamond Plating - Increases Surface Area of Interconnect for Low Ohmic contact (~5 millohms) and allows for Multiple Penetration Points into Solder Ball. The Net Effect is to substantially decrease Skin Effect Loss at Interconnect
Nominal losses stem from the typical minimum interconnect surface area for BGA and other MLF type packages. However, the Conductive Diamond Plating (CDP) interposer minimizes these skin effect losses by maximizing contact area and penetration, thereby reducing transmission loss across the connection. TDR data of both Solder Ball and Interposer interconnects demonstrates the enhanced performance of the interconnect, with the interposer present. Not only does this data indicate superior performance for the CDP interposer as a socket solution, but also illustrates better performance when compared to a soldered connection.
Inductance is Reduced With Mulitple Contact Points
Each of the electrically conductive coated diamonds represent a microscopic probe tip that makes contact with the solder ball. Each tip represents a small amount of inductance (L) in parallel, for a mathematical reduction of total inductance at the CDP point.
In this test case, the measured Insertion and Return Loss shows a 4 GHz resonance at the solder BALL causing PCIX Return Loss failure below 6 GHZ. When a CDP socket was employed, the Return and Insertion was measured beyond 12 GHz, without any additional engineering changes to the board